Questions entretien Analog Design Engineer chez Intel Corporation | Glassdoor.fr

Questions entretien Analog Design Engineer chez Intel Corporation

Entretiens chez Intel Corporation

19 Avis sur les entretiens

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Utile (1)  

Entretien de Analog Design Engineer

Employé anonyme - Boston, MA (États-Unis)
Offre d'embauche acceptée
Expérience positive
Difficulté moyenne

Candidature

J'ai postulé en ligne. J'ai passé un entretien à Intel Corporation (Boston, MA (États-Unis)) en mars 2016.

Entretien

2 phone interviews and 1 full day onsite. the onsite was taken on skype to balance the budget. It was a good experience.you could write on blackboard and answer and it was a live video though my video got stuck.

Questions d'entretien d'embauche

Autres avis d'entretien pour Intel Corporation

  1.  

    Entretien de Analog Design Engineer

    Candidat à l'entretien anonyme
    Aucune offre d'embauche
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé en ligne. J'ai passé un entretien à Intel Corporation.

    Entretien

    It was a phone interview that would test how my qualifications would best fit the position. The interview lasted for 20 mins which was scheduled for 30 minutes. I was told that I would be given the result of the interview in 7 days. I have answered almost all the questions during the phone interview. Having not heard even after 10 days I have contacted the person who interviewed me. I was told that they are interviewing few more candidates and would get back to me once they decide a decision and path forward. It has been a month and a half from the date of the phone interview and I have not heard anything back from the person.

    Questions d'entretien d'embauche

    • Given two plates of a capacitor connected to a voltage source which side of each plate would be charged and what would be the polarity?   1 réponse
    • How would you represent practical capacitor using RLC elements?   Répondre à cette question
    • A question upon my project went into the details of what kind of op-amp being used in the amplifier and how the performance is achieved   Répondre à cette question
    • What is DIBL?   Répondre à cette question
    • Few questions on the MOSFET operation including the DIBL effect, and how vt of a MOSFET is improved when technology is being scaled down. How would one increase the gate capacitance   Répondre à cette question

  2. Utile (1)  

    Entretien de Analog Design Engineer

    Employé anonyme - Fort Collins, CO (États-Unis)
    Offre d'embauche acceptée
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé via une recommandation d'un employé. Le processus a pris 2 semaines. J'ai passé un entretien à Intel Corporation (Fort Collins, CO (États-Unis)) en février 2017.

    Entretien

    Applied online and got a referral.
    Telephonic (normal call) interview which lasted for around 40 minutes - had technical and behavioral questions. Very friendly hiring manager - more like a conversation than an interview.

    Questions d'entretien d'embauche

    • Asked me to describe a relevant project on my resume - Design of a 2 stage op amp.   1 réponse
    • Comparison between NAND & NOR gates - capacitance, area considerations, CMOS equivalent circuit. Was asked which one was better among the two.   Répondre à cette question
    • Computer architecture basics: What is a memory hierarchy? What's the need for such a system?   2 Réponses
  3.  

    Entretien de Analog Design Engineer

    Candidat à l'entretien anonyme - Santa Clara, CA (États-Unis)
    Aucune offre d'embauche
    Expérience négative
    Entretien facile

    Candidature

    J'ai postulé via un établissement de l'enseignement supérieur ou universitaire.. Le processus a pris 3 semaines. J'ai passé un entretien à Intel Corporation (Santa Clara, CA (États-Unis)) en juin 2016.

    Entretien

    The interview was good. Most of the interviewers seemed to like me - except for the hiring manager (it seems). He was bit arrogant or let's just say that he wanted to hear the answers that he wanted to - without giving any regard to any other answers that might have been better to his existing design questions. I think because layoffs were in the air, back in June-July of 2016, he shrugged off saying that they have a "hiring freeze". Would have been a nightmare if I had to work under him. The process took 3 weeks.

    Questions d'entretien d'embauche

    • Lab probing
      MOS amplifier configuration
      Some layout related questions   3 Réponses

  4.  

    Entretien de Analog Design Engineer

    Candidat à l'entretien anonyme - Folsom, CA (États-Unis)
    Aucune offre d'embauche
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé en ligne. Le processus a pris 2 semaines. J'ai passé un entretien à Intel Corporation (Folsom, CA (États-Unis)) en janvier 2015.

    Entretien

    It was an average level interview. There was two phone screen and 1 onsite interview. The process was quick. The phone screening included basic cmos questions and the onsite was more towards timing analysis and verilog vhdl questions

    Questions d'entretien d'embauche

    • They asked questions mostly related to VLSI design and verilog vhdl   1 réponse

  5.  

    Entretien de Analog Design Engineer

    Candidat à l'entretien anonyme
    Aucune offre d'embauche
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé via une recommandation d'un employé. J'ai passé un entretien à Intel Corporation.

    Entretien

    Phone interview followed by an in-person interview. The interview process took two months. The interview is well organized. Four one-on-one round. Each round is about 45 minutes. Device physics, logical design, inverter design, RC questions were asked

    Questions d'entretien d'embauche

    • device physics, Rc delay, Logical questions   2 Réponses

  6.  

    Entretien de Analog Design Engineer

    Candidat à l'entretien anonyme - Oregon City, OR (États-Unis)
    Aucune offre d'embauche
    Expérience neutre
    Difficulté moyenne

    Candidature

    J'ai postulé en ligne. Le processus a pris 2 semaines. J'ai passé un entretien à Intel Corporation (Oregon City, OR (États-Unis)) en janvier 2016.

    Entretien

    I applied online, got a mail for phone interview. I had onsite interview after 2 weeks. Phone interview was pre-screening, mostly basic question. On site interview had 7 technical rounds

    Questions d'entretien d'embauche


  7. Utile (3)  

    Entretien de Analog Design Engineer

    Employé anonyme - Folsom, CA (États-Unis)
    Offre d'embauche acceptée
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé via un établissement de l'enseignement supérieur ou universitaire.. Le processus a pris 5 semaines. J'ai passé un entretien à Intel Corporation (Folsom, CA (États-Unis)) en avril 2012.

    Entretien

    got information from my college job board for an internship position. after a phone screener, they notified me that the internship position was no longer available, but they had an opening for a full-time employee instead. they arranged for an on-site interview which was about 6 hours of technical questions with many teams and a lunch break.
    the technical questions were mostly about digital design questions, even though everything in my resume's education history/projects were analog. the final interviewer noticed the discrepancy and called an analog team lead to give me an additional interview.
    I was really fortunate for this as I was completely out of my element for digital questions (even though they were pretty standard digital questions). I was able to convince the analog interviewer that I was not as dumb as I had sounded in all the digital interviews and they offered me a position with the analog team a few weeks later.

    Questions d'entretien d'embauche

    • Digital: gate-level combinational logic to realize various functions, timing analysis for sequential logic, various fan-out loading questions (I don't remember too many details about this line of questioning, sorry)

      Analog: standard circuit design questions including: transistor equations, single transistor amplifiers, current mirrors, cascoding, diff-pairs, op-amps, analog layout pitfalls, and basic process-related concepts (parasitics, body effect, threshold voltage trick questions, etc).   Répondre à cette question
  8.  

    Entretien de Analog Design Engineer

    Candidat à l'entretien anonyme
    Aucune offre d'embauche

    Candidature

    J'ai postulé via un établissement de l'enseignement supérieur ou universitaire.. J'ai passé un entretien à Intel Corporation.

    Entretien

    The first round is a phone interview, call was on time.
    Questions intend to test thinking ability and knowlegde.
    1.) Question on RC circuits
    2.) What happens when vdd and gnd of an inverter are swapped?
    3.) Draw the waveform of the output when a constant current source is connected to a capactor initially uncharged.

    Questions d'entretien d'embauche

    • What happens when vdd and gnd of an inverter are swapped?   1 réponse

  9.  

    Entretien de Analog Design Engineer

    Candidat à l'entretien anonyme - Urbana, IL (États-Unis)
    Aucune offre d'embauche
    Expérience neutre
    Difficulté moyenne

    Candidature

    J'ai postulé via un établissement de l'enseignement supérieur ou universitaire.. Le processus a pris 1 jour. J'ai passé un entretien à Intel Corporation (Urbana, IL (États-Unis)) en septembre 2019.

    Entretien

    It was a phone interview. The next process presumably would be another phone or on-site interview. The interviewer called over phone and asked questions for about 30 mins. But it was scheduled for 45-60 mins. Questions were relevant.

    Questions d'entretien d'embauche


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