Question d'entretien d'embauche Intel Corporation: Vlsi, setup and hold time vio... | Glassdoor.fr

Question d'entretien d'embauche

Entretien de Physical Design Engineer(Candidat étudiant) Fort Collins, CO (États-Unis)

Vlsi, setup and hold time violation, pipeline, logic design

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Réponse de l'entretien

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Setup time: the time interval before the clock transition , where the clock signal has to be stable . So that the functionality of the flop is proper.

Hold time : the time interval after the clock transition , where the clock signal has to be held stable , so that the flop will respond properly to the given input.

Himaja, le 30 juil. 2017

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