Questions entretien chez Xilinx | Glassdoor.fr

Questions entretien chez Xilinx

Entretiens chez Xilinx

206 Avis sur les entretiens

Expérience

Expérience
64%
23%
13%

Obtenir un entretien

Obtenir un entretien
46%
19%
16%
9
6
3
1

Difficulté

3,0
Moyenne

Difficulté

Difficile
Moyenne
Facile
  1. Utile (1)  

    Entretien de Intern

    Employé anonyme
    Offre d'embauche acceptée
    Expérience positive
    Entretien dificile

    Entretien

    2 phone interviews one day after the other which were both technical and behavioral in nature. Second was a little more technical than the first. Problems were done on google docs

    Questions d'entretien d'embauche


  2.  

    Entretien de Software Engineer()

    Candidat à l'entretien anonyme - Tempe, AZ (États-Unis)
    Aucune offre d'embauche
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé via un recruteur. J'ai passé un entretien à Xilinx (Tempe, AZ (États-Unis)).

    Entretien

    I got this opportunity by directly contacting the manager I happened to connect with on Linked in. This was a 45 min interview mainly based on my projects in the resume and some coding questions . 2 coding questions . I was provided with a online editor for the same .

    Questions d'entretien d'embauche

  3. Utile (1)  

    Entretien de Verification Design Engineer

    Candidat à l'entretien anonyme - San Jose, CA (États-Unis)
    Offres d'embauche déclinées
    Expérience négative
    Difficulté moyenne

    Candidature

    J'ai postulé en ligne. Le processus a pris 3 semaines. J'ai passé un entretien à Xilinx (San Jose, CA (États-Unis)) en septembre 2019.

    Entretien

    I applied on the website, did a phone interview, then did an onsite. They told me they moved fast and to expect my results soon. I thought I didn't do well, so when they didn't email me for a week, I just assumed I didn't pass.

    3 weeks later, out of the blue, they called me saying that wanted to offer me the position. They hesitated to give me exact details, saying they wanted to know if I would accept on the spot. They were very pushy about this, and came off very unprofessional. When I couldn't accept on the spot, they seemed really impatient and didn't want to give me much time to think about it. I ended up not taking their offer.

    Questions d'entretien d'embauche

    • for the onsite, 45 min each of the following:

      - introductory, asking about my resume, background, etc.
      - OOP concepts and questions
      - digital design/logic puzzle questions
      - introductory signals and systems
      - clock domain crossing questions
      - what cases you need to verify a given design   Répondre à cette question

  4.  

    Offre d'embauche acceptée
    Expérience positive
    Difficulté moyenne

    Entretien

    The interview process moved very quickly and involved a technical phone screen followed by 5 technical/behavioral interviews with the team. Technical questions were a mix of coding and seeing how familiar you are with certain concepts.

    Questions d'entretien d'embauche

    • I won't disclose specific questions out of respect, but freshen up on scheduling, process synchronization, inter-process communication, memory management, interrupt handling, DMAs, OS and RTOS concepts, and anything else that might be relevant to the position.   2 Réponses
    • For behavioral questions, they're mostly looking to see how you solve problems, your own work history, and how interested you are in the position.   1 réponse

  5.  

    Entretien de Design Engineer

    Candidat à l'entretien anonyme - San Jose, CA (États-Unis)
    Aucune offre d'embauche
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé via une recommandation d'un employé. Le processus a pris 5 jours. J'ai passé un entretien à Xilinx (San Jose, CA (États-Unis)) en mai 2019.

    Entretien

    1 phone interview. 6 rounds of 45 mins on-site interviews. They were very accommodating. The interviews were continuous except for a 30 mins lunch break after 3 rounds. the interview happened smoothly and on time.

    Questions d'entretien d'embauche

    • Questions from my resume.
      Asked me to decipher a systemverilog design.
      Asked me to design a automated garage door.   Répondre à cette question

  6.  

    Entretien de IC Design Engineer

    Candidat à l'entretien anonyme
    Aucune offre d'embauche
    Expérience neutre
    Difficulté moyenne

    Candidature

    J'ai postulé via une recommandation d'un employé. Le processus a pris 4 jours. J'ai passé un entretien à Xilinx.

    Entretien

    He concentrated on clock tree synthesis, friendly. It was an interview with team manager. One question was unclear. He discussed resume and background in the first ten minutes. More of back end job.

    Questions d'entretien d'embauche


  7. Utile (2)  

    Entretien de Design Engineer

    Candidat à l'entretien anonyme - San Jose, CA (États-Unis)
    Offres d'embauche déclinées
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé en ligne. Le processus a pris 3 semaines. J'ai passé un entretien à Xilinx (San Jose, CA (États-Unis)) en mars 2019.

    Entretien

    Directly contacted by a member of the team for phone interview. After the phone interview, I was called on-site for 6 rounds of 45 minute sessions with teams members and a director, including HR round. The process was fast, with excellent transparency, and a very accommodating manager. The roles and the projects for the future were exciting but I decided to take a different offer.

    Questions d'entretien d'embauche

    • Timing arcs, Perl script, Digital Design basics, FFs, Latches, SRAM.   1 réponse
  8.  

    Entretien de Verification Design Engineer

    Employé anonyme - San Jose, CA (États-Unis)
    Offre d'embauche acceptée
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé en ligne. Le processus a pris +4 semaines. J'ai passé un entretien à Xilinx (San Jose, CA (États-Unis)) en mars 2019.

    Entretien

    I applied online. The process took a month. One phone screen. The feeed back is generally given within a week. This is followed by five onsite interviews. The results are given in a week or two.

    Questions d'entretien d'embauche

    • Verification of different designs. Some basic rtl design questions. Project related questions. UVM based questions   Répondre à cette question

  9. Utile (1)  

    Entretien de Design Engineer

    Candidat à l'entretien anonyme
    Offres d'embauche déclinées
    Expérience positive
    Difficulté moyenne

    Candidature

    J'ai postulé en ligne. J'ai passé un entretien à Xilinx.

    Entretien

    interview i attend was an onsite interview at the head office. It is a great place to work. people are friendly and helpful.

    interview process conducted on time according to given schedule.

    Questions d'entretien d'embauche


  10. Utile (2)  

    Entretien de Design Engineer

    Employé anonyme - San Jose, CA (États-Unis)
    Offre d'embauche acceptée
    Expérience positive
    Entretien facile

    Candidature

    J'ai postulé en ligne. J'ai passé un entretien à Xilinx (San Jose, CA (États-Unis)) en janvier 2019.

    Entretien

    1 Telephonic Interview + Day long On-site Interview Process(4 TIs + HR)

    Overall Topics to prepare:
    Digital(Muxes, FFs, Timing Params, Synchronizers and Asyn FIFOs, Clock domain crossings)
    Verilog Coding Basics (Case, if-else, Practical Design problems)
    SV Basics(Tasks Process, Fork Join)
    Comp Arch(Pipelining, Load store Arch)
    Scripting(Python/ Perl/ Tcl anyone)

    Questions d'entretien d'embauche

    • #Telephonic Round:
      Simple digital, verilog, timing Qs (30mins)

      #Onsite Interview:(45 mins each)
      Round 1:
      Simple Digital Qs, Verilog code (Case , if-else difference, Blocking-Nonblocking difference, Unintensional latch problem), Power reduction techniques(Clk Gating) + extended Qs on same topic
      Previous work related Qs , Module's overall working

      Round 2:
      Verification basics like:
      What is fork -Join?
      Tasks and fns
      Pass by value , Pass by Refn
      Logic behind Linked list entry removal(How address pointer is changed)

      Round 3:
      Verilog code for shift left, shift right, parallel load functionality
      Some logical puzzales
      Digital concepts like basic gates using Mux, Gate Reduction etc.

      Round 4
      More on Power reduction
      Setup and Hold time eqs and Violation removal techniques
      Diffn betn: Glich and Jitter and skew   Répondre à cette question

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