Questions d'entretiens - Design engineer intern


Questions d'entretien pour Design Engineer Intern partagées par les candidats

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On a demandé à un ASIC Design Engineer - Intern...10 juillet 2013

Design clock switchers without any glitch.

2 réponses

You can find the answer online.

use a mux with synchronizer


Give me an example of asynchronous finite state machine.

1 réponses

A simple state machine that flip flops between 0 and 1 that depends on the input. Moins

Intel Corporation

What is a fomal verification system

1 réponses

after the simulation when the schematic is made in the synthesis it is taken in parts and the logic verification is done thoroughly. it is different from gate level testing. Moins


What should be the size of the buffer in a FIFO receiving data packets at a certain rate?

1 réponses

read rate * read clk- write rate * write clk

Texas Instruments

Asked to perform circuit analysis.

1 réponses

I tried to perform as best as I could.


What should be the size if it is receiving data and also loosing some packets ?

1 réponses

need to know the burst size and read/write rate

Amazon Lab126

Why there is a gap between USB head and the side wall of the laptop?

1 réponses



Where do you see yourself in 5 years?


Tell me a bit more about the projects you’ve worked on while in college?


Cantilever beam questions; change in stiffness etc.

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