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Questions d'entretiens - Design engineer intern
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Questions d'entretien pour Design Engineer Intern partagées par les candidatsPrincipales questions d'entretien
On a demandé à un ASIC Design Engineer - Intern...10 juillet 2013
Design clock switchers without any glitch.
2 réponses↳
You can find the answer online.
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use a mux with synchronizer
Give me an example of asynchronous finite state machine.
1 réponses↳
A simple state machine that flip flops between 0 and 1 that depends on the input. Moins
What is a fomal verification system
1 réponses↳
after the simulation when the schematic is made in the synthesis it is taken in parts and the logic verification is done thoroughly. it is different from gate level testing. Moins
On a demandé à un ASIC Design Engineer Intern...14 mars 2010
What should be the size of the buffer in a FIFO receiving data packets at a certain rate?
1 réponses↳
read rate * read clk- write rate * write clk
On a demandé à un Analog Design Engineer Intern...24 janvier 2022
On a demandé à un ASIC Design Engineer Intern...14 mars 2010
What should be the size if it is receiving data and also loosing some packets ?
1 réponses↳
need to know the burst size and read/write rate
On a demandé à un Product Design Engineer Intern...18 février 2014
On a demandé à un Design Engineer Intern...27 juillet 2020
Where do you see yourself in 5 years?
On a demandé à un Electrical Design Engineer Intern...17 janvier 2021
Tell me a bit more about the projects you’ve worked on while in college?
