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      PRIMESOC Technologies

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      FPGA Design Engineer : entretien chez PRIMESOC Technologies

      Question d’entretien chez PRIMESOC Technologies

      Entretien pour FPGA Design Engineer

      About the Verilog Project asked to write the Code and explain it..

      Réponse à la question d'entretien

      Utilisateur anonyme

      8 avr. 2025

      I wrote the simple code of my project and explained, The interviewer got to know I have knowledge of Verilog and gave the offer.. Just give the straight away so that interviewer won't thinks you don't have knowledge of it

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