I don't see it being possible with three standard 4-1 muxes... Using 4, this question is straight forward... The two selects of each mux are your 8 inputs... tie out put of each mux to the (11) case input to the mux.

We need 3 4:1 MUX and a And gate. Are we allowed to use 'and' gate?

A to H are the 8 inputs. For the first 2 muxes we can have GH as select bits with all their inputs tied to 0. Connect output of these muxes to the first 2 input lines of third mux. Tie the third input to 0. Now we care only about the 4th input line when EH are both 1s. We can derive an expression and connect it to the 4th input line of third mux. job done.

mux1: (0,1,2)==0 and (3)=C with sel: AB ====OUT1==ABC mux2: (0,1,2)==0 and (3)=D with sel: EF ====OUT1==DEF short ABC and DEF as---if any one of them is 0---it will be zero----if both of them are 1---it will be one mux3: (0,1,2)==0 and (3)..shorted out1 and out2 with sel:GH===out:ABCDEFGH

I can only make it 7 bits with that explenation.

tie 3 0's to the three inputs of initial 2 4x1 mux, the 3rd input be an actual input, 2 sel be 2 inputs. feed the output of the results of the two muxes as sel to the 3rd mux and tie the last inputs to actual inputs and top two inputs to 0's.

Not so. You only need 2 4:1 muxes. Have the output of the first be the select to the second. 8 input and gate.