Genral questions
1 setup time hold time
2 verilog basics
verilog caculating (a+b)/2 or (a+b+c+d)/4, how to round
3 what 's the use of arbitrary
4 vending machine state machine
5 architecture pipeline
J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 1 jour. J'ai passé un entretien chez Ambarella en mars 2014
Entretien
Phone interview, approximately 1 hour. First the director introduced what his group is doing and asked one of my course project. Then he requested to write Verilog codes, including switching a and b in one clock cycle, explaining blocking and non-blocking, and implementing FSM of a pattern detector.
