`timescale 1ns / 1ps module FIFO(clk, rst, r_e, w_e, overflow, underflow, data_in, data_out); input clk, rst, r_e, w_e; input [7:0]data_in; output overflow, underflow; output reg [7:0]data_out; reg [3:0] r_p, w_p, count; reg [15:0]fifo[7:0]; assign overflow = (count == 4'b1111); assign underflow = (count == 4'b0000); always@(posedge clk) begin if(rst) //reset is pressed begin //processing from the beginning count <= 4'b0000; r_p <= 4'b0000; w_p <= 4'b0000; end end always@(posedge clk) begin if(w_e && !overflow)//write data in FIFO begin fifo[w_p] <= data_in; w_p <= w_p + 1'b1; count <= count + 1'b1; end else if(w_e && r_e)//simultaneous reading and writing data begin fifo[w_p] <= data_in; w_p <= w_p + 1'b1; count <= count; end end always@(posedge clk) //reading and writing process continued begin if(r_e && !underflow)//read data from FIFO begin data_out <= fifo[r_p]; r_p <= r_p + 1'b1; count <= count - 1'b1; end else if(w_e && r_e)//simultaneous reading and writing data begin data_out <= fifo[r_p]; r_p <= r_p + 1'b1; count <= count; end end always@(posedge clk) //overflow and underflow begin if(w_p == 4'b1111 || count == 4'b1111)//overflow condition begin overflow <= 1'b1; end else if(r_p == 4'b1111 || count == 4'b0000)//underflow condition begin underflow <=1'b1; end end always@(posedge clk) //data bypass condition begin if(w_p == r_p) begin data_out <= data_in; count <= count; w_p <= w_p; r_p <= r_p; end end endmodule