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      Maxeler Technologies

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      Entretiens chez Maxeler TechnologiesEntretiens d’embauche pour FPGA/Hardware Engineer chez Maxeler TechnologiesEntretien chez Maxeler Technologies


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      Entretien pour FPGA/Hardware Engineer

      19 août 2015
      Candidat à l'entretien anonyme
      Aucune offre
      Expérience positive
      Entretien difficile

      Candidature

      J'ai passé un entretien chez Maxeler Technologies

      Entretien

      First round is a telephone interview with 30 min HR questions and about 1 hour technical questions. Second round is an online assessment, followed by a programming test quest. Failed to attend the last round interview which is a face to face interview.

      Questions d'entretien [1]

      Question 1

      basic questions about FPGA
      Répondre à cette question

      Autres retours d’entretien d’embauche pour un poste comme FPGA/Hardware Engineer chez Maxeler Technologies

      Entretien pour FPGA/Hardware Engineer

      25 avr. 2015
      Candidat à l'entretien anonyme
      Londres, Angleterre
      Aucune offre
      Expérience positive
      Entretien difficile

      Candidature

      J'ai postulé en ligne. Le processus a pris 6 semaines. J'ai passé un entretien chez Maxeler Technologies (Londres, Angleterre) en janv. 2015

      Entretien

      First step, phone interview (half an hour with human resources and one hour with an engineer of the team). The HR interview was very simple (What do you know about Maxeler Technologies? Why do you want to work for us? etc) and the interview with the engineer was more complicated but still okay. He asked a lot of questions about my previous experiences. He also asked me what do I know about Maxeler technologies. And then he switched on technical questions. Some of them appeared to be tricky (I was a graduate engineer at that time) and other were more basics. Second step, they send you an exercise where you have to write a small software that can process some data files that they give you. And then you have to reuse your software to generate a specific .bga file. Good thing: You are free to use any language that you want. At the same time, they send you a link for a shl IQ test. The software and the shl test have to be done whithin three days. Third step, they call you to debrief on the results of your program. The questions asked by the engineer appeared to me to be difficult (again, I was a graduate). They were more optimisation questions regarding my program (For example: How could you use an integer and still encode a number bigger than the limit of the integer or something like that?). Fourth and last step, they invite you for an onsite interview. I arrived at the HQ in London at 12:30. You begin with a small visit of the offices with the head of the hardware team and then interview with him. We went through all my application process (first phone interview, software and shl results, second interview,...) and then asked me some technical questions regarding FPGAs. He showed me several schematics and asked to say what is it and explain it. And then, second interview with a software engineer where he asked me to write another program regarding nodes and basic calculations in 90 minutes and then debrief with him. The third interview with another hardware engineer and he asked two simple questions regarding some logical design. The fourth interview was with the same guy that interviewed me on phone (first phone interview) and he asked some more tricky questiosn regarding digital design (Metastability, FIFOs,...). The fifth and last interview was with an application engineer and he asked me some reasoning questions. Average questions and the guy helps you a little bit. They told me that I also should have met the CEO but he was very busy on that day. So, to summarize, arrived at 12:30. Had 5 interviews with 5 different engineers and they released me at 19:00. After two weeks, I sent an email to the human resources lady to know if they already have the results of my interview or not. Two hours later, she replied to me telling me that they decided to not pursue the recruitment process with me... I keep asking myself that, if I didn't send that email, would I have one day received an answer? Who knows... Another disappointing thing from them is that they refused to tell me why I didn't get the job... They claimed that "it is our company mandate that we do not provide feedback as to why the application was refused". Worst thing to say to a young graduate that needs to is making mistakes and needs to know what are his mistakes. But, generally speaking, except those two things, this interview was an amazing experience, I learned a lot and the people that interviewed me were amazing guys.

      Questions d'entretien [4]

      Question 1

      First phone interview: - What is the difference between the cache memory and the global memory? - What does an FPGA cell contain? - What kind of hard blocks can you find in an FPGA? - What does a DSP core contain? - What will be the maximum size of a multiplexer if I have a 6 inputs lookup table? - How many lookup tables do I need to build a 64 inputs multiplexer? - What is a linking list? - What is the polymorphism? - What do you know about threads? - On linux, which command do you have to write to copy a full folder containing other folders and files? - You need to write a compiler, which language would you use?
      Répondre à cette question

      Question 2

      First onsite interview: - Showed me a Stratix Altera FPGA ALM and asked what is it, which manufacturer and which model - Same but with a Xilinx one - Asked me to explain a document regarding some state machine explanation by Altera - Showed me an Altera transceiver schematic and asked me to explain it and detail each block of it - Showed me a general schematic of an FPGA and asked me to define each hard block that was present on it - Showed me a diagram of CVP (Configuration via Protocol) from Altera and asked to explain it
      Répondre à cette question

      Question 3

      Third onsite interview: - You have a black box that takes two numbers in two different inputs and gives you the biggest and the lowest number on two different outputs. Use this black box to build the same but with 4 numbers input - You have a synchronous that receive on each block pulse a new bit that you add the serie of bits received on each clock pulse. Due to this add of bit, build a system that is able to say if, on each clock pulse, the new number is divisible by 5 or not
      Répondre à cette question

      Question 4

      Fourth onsite interview: - Explain me the metastability - How can you cross different clock domains - Explain me how a FIFO does work and how is it built Fifth onsite interview: - Reasoning questions. Too much complicated to explain by text, sorry guys!
      1 réponse
      9

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