Questions posées lors d’un entretien d’embauche pour Staff II IC Design Engineer chez Broadcom

R1: Design Full adder with two half adders? Explain one sorting Algorithm? Describe few test cases you would write for testing 32*8 k FIFo? Design AND and OR gates using 2:1 MUX? The Difference between implementation of Level sensitive and Edge Sensitive sequential circuits? Define State Machines? Design counter in Verilog? and Few puzzles R2: Questions on previous Job project? Few real life application puzzles like how traffic signals function (i.e logic to decide the status of a signal)? Few general puzzles?(use minimum functionality to design mathematical models) Which gate is used to compare two similar signals? - XOR gate. Verilog code was given draw signals at various time intervals? Fork and Join_any, Join_None, Join_All implementation? R3(Toughest Round): Design FIFO in Verilog? Design Timer block in Verilog? Explain FSM signal? Design any model of FSM? Mealey V/S Moore Machine? Design a Mealey machine in Verilog? The Difference between Reg and Net in Verilog? Two initial blocks executed at a time? Default values of Reg, Wire? R4(OOPS - I worked as software developer): Various principles of OOPS? Implement Inheritance? Implement Polymorphism? Pass by reference in Java? Difference between Malloc and Calloc? Garbage Collector in Java? Virtual(Abstract in Java) Classes? Use of Static modifier? How different variables are stored in Memory? Accessibility modifiers - public, default, protected, private? R5: A System was given and functionality explained, then asked to write test cases(basic and corner cases)?