Its an hour long interview, asked basic questions on verilog, systemverilog, oops, little bit of linux. There were considerate if I didnt know answer to any question and explained me briefly.
Questions d'entretien [1]
Question 1
design cycle and verification plan, polymorphism, inheritance, diff between python and perl, which to use when, blocking vs non blocking assignment, X vs Z in verilog, UVM phases, scoreboard vs monitor, etc
J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Intel Corporation (Bengaluru) en févr. 2026
Entretien
directly based on resume shortlist and online test. it was on campus hiring for Mtech. overall interview is descent and not much hard. initially they asked about my project in detail.
Questions d'entretien [1]
Question 1
Verilog code for MUX and C++ for matrix multiplication.
J'ai postulé via un établissement d'enseignement supérieur ou universitaire. J'ai passé un entretien chez Intel Corporation
Entretien
Scheduled a 45min interview. Asked both about technical and behavioral questions. Interviewer is very friendly. Technical questions mostly focus on digital circuit, logic design, FSM, and some knowledge about analog circuit.
