They ask about digital & analog electronics and verilog
In Analog they will ask about filters, in digital they ask about flip flops and MUXs . In Verilog they ask basic syntax and Clock tree synthesis
J'ai passé un entretien chez Synopsys (Ottawa, ON)
Entretien
It was a smooth process, mostly technical problems, no tricky questions. Mostly asked about previous project on resume, with some coding questions at the end. Total 4hr with 4 different engineer/manager
The interview process consisted of two rounds. The first was a technical screen focusing on Verilog and RTL design. The second was a behavioral interview with the manager. nice processes overview
J'ai postulé via la recommandation d'un employé. J'ai passé un entretien chez Synopsys en mars 2025
Entretien
hard. fifo's n all. and other designing questions. muxes, gates, cdc n all. designing n other implementation questions are their . tough questions were their. U get designing to the best.
Questions d'entretien [1]
Question 1
ok. fifo..design n implementation.and other designing questions
