What makes an AI model useful in the fab? Corporate VP David Fried shares how we accelerate the development of AI-based equipment models using data and how these models guide real-world tool optimization via Semiconductor Engineering.
Did you know that switching from tungsten to molybdenum in chip interconnects can reduce contact resistance by up to 50%? In this Semiconductor Engineering article, Corporate VP & GM Dr. Kaihan Ashtiani explains how this shift improves performance and reliability for AI chips operating at extreme scales.
With Semiverse® Solutions, engineers can virtually visualize complicated 3D structures like never before. Read our blog post to see how virtual fabrication transforms semiconductor development.
Our collaborative robot Dextro™, a historic first in the semiconductor industry, won a Best of Sensors Award! We let Dextro™ shed light on this achievement in a recent blog post. Check it out.
From learners to leaders, the first cohort of our Microscopy Technician Training Program just graduated! Through this program with Portland Community College, we help students gain hands-on experience with the same equipment used in advanced manufacturing. In just eight weeks, participants learned how to navigate complex imaging tools and apply that knowledge to real-world challenges. It’s all part of building a stronger, more skilled tech workforce in Oregon. Read the blog for more.
Not all yield loss is visible on the surface. Mechanical deformation during fabrication can quietly alter device dimensions, until performance takes a hit. We use virtual fabrication with SEMulator3D® to simulate stress, spot hidden risks, and refine process windows before a single wafer is built. Read our blog post to learn more.
How do you etch the future into silicon? With DirectDrive®, we introduced a new way to control plasma, built through years of joint research with the National Science Foundation (NSF), UCLA, and the University of Michigan. It’s not just about precision at the atomic level. It’s about rethinking how ideas move from an experiment to high-volume chipmaking. See the power of long-term collaboration via the NSF article.
As transistors shrink into the angstrom era, power integrity and thermal management become critical. Backside power delivery networks (BSPDNs) offer a solution by rerouting power through the wafer’s backside, which reduces congestion and improves efficiency. Learn how BSPDNs influence mechanical stress in gate-all-around (GAA) transistors and what it means for future chip performance.
As demand for advanced packaging increases, new substrate materials and process innovations are essential for achieving the interconnect density required for AI, high-performance computing, and 5G applications. Managing Director for Advanced Packaging Chee Ping Lee explores these shifts in a Semiconductor Engineering article.
NF3 has a high global warming potential, but smart optimizations can make a difference. By working with STMicroelectronics, we achieved a 32% reduction in CO2e emissions through optimized chamber cleaning — a step toward a more sustainable future. Learn more.
