J'ai postulé via un établissement d'enseignement supérieur ou universitaire. Le processus a pris 1 semaine. J'ai passé un entretien chez Qualcomm (Bengaluru) en août 2020
Entretien
asked questions on VLSI physical design, questions on cmos inverter, different cells used in physical design, what projects and experience i have in this field, some questions related to digital design
4 interviewers.
Basics of physical design /cpu architecture/experience based questions/tcl scripting/timing analysis/block closure /techniques/previous wrk exp/ drc analysis related questions/ tool related questions/ example
Based questions “how would you solve this?” Kind of questions
Questions d'entretien [1]
Question 1
Explain the challenges involved in previous tapeout
J'ai postulé en ligne. J'ai passé un entretien chez Qualcomm (Austin, TX) en sept. 2025
Entretien
One hour and loop with 5 people each round focusing on eache step of physical design flow and cadence tools. I have a thesis on RISC V low voltage pd so they asked about that more
J'ai passé un entretien chez Qualcomm (San Diego, CA)
Entretien
Application via Qualcomm careers or referral.
Recruiter may reach out for basic screening:
Your background, tools used (ICC2, PrimeTime, RedHawk, etc.)
Areas of expertise: floorplanning, CTS, routing, STA, DRC, EMIR, etc.
Experience with multi-VDD, ECOs, hierarchical designs, colored flows, etc.
Technical Phone Interviews (1–2 rounds)
Each round typically lasts 45–60 minutes.
Questions d'entretien [1]
Question 1
Walk me through how you approach floorplanning for a block.
How do you handle placement of macros and standard cells around them?
What considerations go into designing a power grid?
How do you handle multi-VDD domains or level shifters?
What are tie-high and tie-low cells and where are they used?